FPGAs are semi-custom devices, which contain a fixed set of gate structures that may be interconnected in a number of ways to achieve a desired logic function. In FPGA's the interconnect pattern is programmed electrically by the user. That is, in commercial applications or in rapid prototyping, FPGA's are useful since these devices can be purchased off the shelf and are flexible enough to be programmed and reprogrammed allowing the system designer to configure the circuit as desired.
FPGAs generally include an array of PLB's (Programmable Logic Blocks). A PLB can be referred to by various names such as a CLB (Configurable Logic Block), a CLE (Configurable Logic Element) or a PFU (Programmable Function Unit). Each PLB is a small programmable logic block which often includes one or more input lines, one or more output lines, one or more latches and one or more LUT's (Look Up Tables).
The LUT can be programmed to perform various functions, for example: general combinatorial logic, control logic or to set up the data path (i.e. interconnect pattern) between the input and output lines.
In this manner, the LUT can determine whether each respective PLB performs general logic, or has a special mode of operation such as an adder, a subtractor, a counter or a register. The actual functionality for each PLB is basically decided by configuration values stored in SRAM memory cells (i.e. latches) for the LUT as well as to make the connections.
These SRAM memory cells are volatile in nature and thereby provide the reconfiguration flexibility desired from a PLB. Using this flexibility, a number of iterations for design purposes can be tried with FPGA devices to eventually achieve the desired specifications of the system. This technique is especially useful for prototyping a new design or product during the development and debugging stages, since the re-programmable nature of the FPGA significantly reduces development and manufacturing costs and time.
On the other hand, an ASIC (Application Specific Integrated circuit) is a less flexible device designed and manufactured to perform a specific function, and requires a relatively large amount of engineering man hours and cost to develop.
Since an FPGA is a flexible and programmable device, it is volatile in nature and requires a large amount of additional circuitry and arrangement for programming, re-programming and storing the information for reprogramming. This additional circuitry is required, for example, when reprogramming the FPGA with different information such as in the prototyping/debugging stages for a product, but has no use once configuration information has been finalized which meets the desired system specifications.
In particular, the additional circuitry increases the total area and complexity of the device if implemented for example on a system board, and increases the amount of silicon used by the FPGA and its additional circuitry when integrated with some ASIC for a PSOC (Programmable System-On-Chip).
ASIC's do not require the additional circuitry and arrangements. Therefore, in the past once a specific configuration has been tested and finalized using programmable logic (i.e. an FPGA), it is then useful to make the system from an ASIC instead of a FPGA. Although the desired configuration of the device will have been finalised, it is still necessary to redesign and manufacture the ASIC to be equivalent to the FPGA, which entails a complex, time consuming and expensive process.
Therefore, once a specific configuration of a programmable logic device is tested and finalized for a system, there is a need to replace the programmable Logic (FPGA) with a hardened circuit, equivalent to an ASIC, which does not have the drawbacks of the additional circuitry of programmable logic or the drain on resources of having to manufacture an ASIC to suit such a purpose.
U.S. Pat No. 6,301,696 describes a method for making an integrated circuit which includes an initial design of an FPGA that can be programmed to implement a desired function and then selecting a specific configuration by hardening the FPGA. This process of hardening is used for increasing the speed of the FPGA by bypassing the on-state resistance of selected transistors with fast metal connections.